Analyze the Tunneling Effect on Gate-All-Around Field Effect Transistor

In this paper we describe the tunneling junction model effect on silicon nanowire gate-allaround field effect transistor using CMOS 45 nm technology. Tunneling effects provides better subthreshold slope, excellent drain induced barrier lowering and superior ION-IOFF ratio.This paper demonstrates the gate controlled tunneling at source of Gate-all-around field effect transistor. Low leakage current (off current) is reported of 2.9uA with considerable power reduction Subthreshold Swing SS is achieved of 46.5 mV/dec .Using Y function series resistance RSD is evaluated.Accurate evaluation of RSD of silicon nanowire Gate-all-around FET is shown linear behavior in inversion region using Y function. Silicon nanowire is considered as better aspect for ultra low power application.